1. Field of Invention
The invention relates to a system for displaying image and a driving method for a liquid crystal displaying device, and, in particular, to a system for displaying image and a driving method for a liquid crystal displaying device that operates in a low voltage.
2. Related Art
In the TFT LCD device (thin-film-transistor liquid-crystal-displaying device), the transistor of the LCD panel includes, according to its structure and manufacturing process, the α-Si TFT (amorphous Si) and Poly-Si TFT (polysilicon). In comparison with the α-Si TFT, the Poly-Si TFT has a lower threshold voltage and a higher electron mobility rate. Therefore, the Poly-Si LCD panel has lower power consumption and is able to integrate with a driving circuit.
Referring to FIG. 1, an LCD device 1 includes a Poly-Si LCD panel 10 and a timing controller 11. A level shifter 12, a scan-line driving circuit 13, a plurality of scan lines 141-14m, a data-line driving circuit 15, a plurality of data lines 161-16n, and a pixel array 17 are formed on the Poly-Si TFT LCD panel 10. The scan-line driving circuit 13 includes a plurality of shift registers 131. The data-line driving circuit 15 includes a plurality of shift registers 151 and a plurality of samplers/holders 152.
The timing controller 11 is manufactured by VLSI processes. It operates at 3V and generates a gate start pulse signal SPG, a gate clock CLKG, a source start pulse signal SPS, a source clock CLKS, and a plurality of data signals DATA. The voltages of these signals are between 0V-3V. Besides, the level shifters 12 operate at 9V. They convert the voltages of these signals from 3V into 9V by using the transistor or resistance load to overcome the threshold voltage (about 1V-4V) of the Poly-Si TFT. Therefore, the Poly-Si LCD panel 10 can process the signals outputted from the timing controller 11 correctly.
The shift registers 131 operate at 9V and the frequency of the gate clock CLKG. They are connected to each other in series and shift the gate start pulse signal SPG to generate scan pulses on the scan lines 141-14m in sequence. These scan pulses conduct TFTs connected with the scan lines 141-14m in the pixel array 17. In addition, the shift registers 151 operate at 9V and the frequency of the source clock CLKS. They are connected to each other in series and shift the source start pulse signal SPS to generate source pulses to the samplers/holders 152 in sequence. The samplers/holders 152 receive the source pulses to sample data signals DATA and output the sample result to the pixel array 17 through the data lines 161-16n in sequence.
Under this architecture as shown in FIG. 1, the circuits formed on the Poly-Si LCD panel 10 operates at 9V. However, in practice, some of these circuits can operate normally at 5V. Referring to FIG. 2, the scan-line driving circuit 13 further includes a plurality of level shifters 132, and the data-line driving circuit 15 further includes a plurality of level shifters 153. The level shifters 11 operate at 5V to convert the voltages of the gate start pulse signal SPG, the gate clock CLKG, the source start pulse signal SPS, the source clock CLKS, and the data signals DATA from 3V into 5V.
The shift registers 131 operate at 5V and shift the gate start pulse signal SPG to generate scan pulses in sequence. The level shifters 132 convert the voltages of the scan pulses from 5V into 9V, and subsequently output these scan pulses to the scan lines 141-14m. The shift registers 151 operate at 5V and shift the source start pulse signal SPS to generate source pulses in sequence. The level shifters 153 convert the voltages of source pulses from 5V into 9V, and subsequently output these source pulses to the samplers/holders 152. The samplers/holders 152 receive the source pulses to sample the data signals DATA in sequence, and output the sample result to the pixel array 17 through the source data lines 161-16n.
Because the shift registers 151 in the data-line driving circuit 15 operate at voltage 5V reduced from 9V, the data-line driving circuit 15 as shown in FIG. 2 is less power consumptive than that as shown in FIG. 1. However, the shift registers 151 of FIG. 2 need additional level shifters 153 to convert the voltages of the output signal from 5V to 9V. Therefore, the data-line driving circuit 15 as shown in FIG. 2 is more expensive. Besides, since the additional level shifters 153 operate at 9V, the data-line driving circuit 15 of FIG. 2 is still power consumptive.
It is therefore a subject of the invention to provide a system for displaying image and a driving method for a liquid crystal displaying device, which can solve the problems described above.